(1) Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the use an alternate etch stop in dual damascene interconnects that improves adhesion between low dielectric constant organic materials, with the etch stop being a low dielectric constant material, consisting of a silicon containing material, which becomes silicon-rich silicon oxide after UV radiation and oxygen plasma.
(2) Description of Related Art
Related Prior Art background patents will now be described in this section.
U.S. Pat. No. 5,830,801 entitled xe2x80x9cResistless Methods of Gate Formation in MOS Devicesxe2x80x9d granted Nov. 3, 1998 to Shiralagi et al. describes a UV method to form a silicon-rich oxide layer. The method is directed toward forming an MOS gate and defining the gate area, which includes forming an oxide mask by positioning a light mask adjacent a surface of a polysilicon layer and exposing the surface through the light mask to a deep ultra violet light in an ambient containing oxygen.
U.S. Pat. No. 6,040,243 entitled xe2x80x9cMethod to Form Copper Damascene Interconnects Using a Reverse Barrier Metal Scheme to Eliminate Copper Diffusionxe2x80x9d granted Mar. 21, 2000 to Li et al. describes dual damascene process comprising: form bottom low K material, form etch stop layer, form top low K and then etch dual damascene opening. Diffusion of copper into dielectric layers due to overetch of the passivation layer is eliminated by a barrier layer. The method can be used to form dual damascene interconnects. Copper traces through an isolation layer are provided overlying a semiconductor substrate. A passivation layer is deposited overlying the copper traces and the isolation layer. A dielectric layer is deposited. A cap layer is deposited. The cap layer and the dielectric layer are patterned to expose the top surface of the passivation layer and to form trenches for the damascene visa. A barrier layer is deposited overlying the passivation layer, the dielectric layer, and the cap layer. The barrier layer is etched though to expose the top surfaces of the cap layer and the passivation layer. The barrier layer isolates the sidewalls of the trenches. The passivation layer is etched through to complete damascene vias. The barrier layer prevents copper sputtering onto the dielectric layer during the step of etching through the passivation layer.
U.S. Pat. No. 6,054,379 entitled xe2x80x9cMethod of Depositing a Low K Dielectric with Organo Silanexe2x80x9d granted Apr. 25, 2000 to Yau et al. teaches a dual damascene process by oxidizing an organo silicon film. A method and apparatus for depositing a low dielectric constant film is described using a reaction of an organo silane compound and an oxidizing gas. The oxidized organo silane film has barrier properties for use as a liner or cap layer adjacent to other dielectric layers. The oxidized organo silane film can also be used as an etch stop or an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organo silane films also provide excellent adhesion between different dielectric layers.
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the use an alternate etch stop in dual damascene interconnects that improves adhesion between low dielectric constant organic materials. In addition, the etch stop material, which is a silicon containing material, is transformed into a silicon-rich silicon oxide after UV radiation and silylation, oxygen plasma.
This invention has been summarized above and described with reference to the preferred embodiments. Some processing details have been omitted and are understood by those skilled in the art. More details of this invention are stated in the xe2x80x9cDESCRIPTION OF THE PREFERRED EMBODIMENTSxe2x80x9d section.